Ch9: ALU, integer representation (twos compliment), IEEE "double" basics.

Ch10: Instruction cycle (Fig. 10.1 on p. 336), Fig 10.2, operands,
types of operations (10.4).

Ch12: 12.3, 12.4

PART IV (Control Unit) summary: p. 569, 570, 572, 597, 598

Parallel Organization:
- pre-examples: piplining, MMX, controllers/DMA/etc, hyperthreads/execution-cores.
- theory: Moore, Amdahl (diminishing returns law), speed-up (ideal/real)
- multiprocessors: memory vs. CPU's (SharedMem vs. Distributed)
- ex-s: SMP, NUMA, cluster, grid
- cluster trade-offs
- interconnects: switch (c.f. hub/router)